Clocks for L5224, L5224_II and L5224_IIA

1.5.2018

OPCode                Bytes |   DC      SC      Coment
----------------------------|-----------------------------
ADD     A,Rr            1   |   1       2
ADD     A,direct        2   |   2       3
ADD     A,@Ri           1   |   1       2
ADD     A,#data         2   |   2       2
ADDC    A,Rr            1   |   1       2
ADDC    A,direct        2   |   2       3
ADDC    A,@Ri           1   |   1       2
ADDC    A,#data         2   |   2       2
SUBB    A,Rr            1   |   1       2
SUBB    A,direct        2   |   2       3
SUBB    A,@Ri           1   |   1       2
SUBB    A,#data         2   |   2       2
INC     A               1   |   1       1
INC     Rr              1   |   1       2
INC     direct          2   |   2       3
INC     @Ri             1   |   1       2
INC     DPTR            1   |   1       1
DEC     A               1   |   1       1
DEC     Rr              1   |   1       2
DEC     direct          2   |   2       3
DEC     @Ri             1   |   1       2
MUL     AB              1   |   1       1
DIV     AB              1   |   1       1
DA      A               1   |   1       1
ANL     A,Rr            1   |   1       2
ANL     A,direct        2   |   2       3
ANL     A,@Ri           1   |   1       2
ANL     A,#data         2   |   2       2
ANL     direct,A        2   |   2       3
ANL     direct,#data    3   |   3       3
ANL     C,bit           2   |   2       3
ANL     C,/bit          2   |   2       3
ORL     A,Rr            1   |   1       2
ORL     A,direct        2   |   2       3
ORL     A,@Ri           1   |   1       2
ORL     A,#data         2   |   2       2
ORL     direct,A        2   |   2       3
ORL     direct,#data    3   |   3       3
ORL     C,bit           2   |   2       3
ORL     C,/bit          2   |   2       3
XRL     A,Rr            1   |   1       2
XRL     A,direct        2   |   2       3
XRL     A,@Ri           1   |   1       2
XRL     A,#data         2   |   2       2
XRL     direct,A        2   |   2       3
XRL     direct,#data    3   |   3       3
CLR     A               1   |   1       1
CPL     A               1   |   1       1
RL      A               1   |   1       1
RLC     A               1   |   1       1
RR      A               1   |   1       1
RRC     A               1   |   1       1
SWAP    A               1   |   1       1
MOV     A,Rr            1   |   1       2
MOV     A,direct        2   |   2       3
MOV     A,@Ri           1   |   1       2
MOV     A,#data         2   |   1       1
MOV     Rr,A            1   |   1       1
MOV     Rr,direct       2   |   2       2
MOV     Rr,#data        2   |   2       2
MOV     direct,A        2   |   2       2
MOV     direct,Rr       2   |   2       2
MOV     direct,direct   3   |   3       3
MOV     direct,@Ri      2   |   2       2
MOV     direct,#data    3   |   3       3
MOV     @Ri,A           1   |   1       1
MOV     @Ri,direct      2   |   2       2
MOV     @Ri,#data       2   |   2       2
MOV     C,bit           2   |   2       3
MOV     bit,C           2   |   2       3
MOV     DPTR,#data24    4   |   4       4
MOVX    A,@Ri           1   |   3       3
MOVX    A,@DPTR         1   |   1/3     2/3     IXD / XDATA
MOVX    @Ri,A           1   |   3       3
MOVX    @DPTR,A         1   |   1/3     1/3     IXD / XDATA
SWAP    A               1   |   1       1
PUSH    direct          2   |   2       3
POP     direct          2   |   2       2
XCH     A,Rr            1   |   1       2
XCH     A,direct        2   |   2       3
XCH     A,@Ri           1   |   1       2
XCHD    A,@Ri           1   |   1       2
MOVC    A,@A+DPTR       1   |   3       3
MOVC    A,@A+PC         1   |   3       3
CLR     C               1   |   1       1
CLR     bit             2   |   2       3
SETB    C               1   |   1       1
SETB    bit             2   |   2       3
CPL     C               1   |   1       1
CPL     bit             2   |   2       3
ANL     C,bit           2   |   2       3
ANL     C,/bit          2   |   2       3
ORL     C,bit           2   |   2       3
ORL     C,/bit          2   |   2       3
MOV     C,bit           2   |   2       3
MOV     bit,C           2   |   2       3
JC      rel             2   |   2/3     2/3     false / true
JNC     rel             2   |   2/3     2/3     false / true
JB      bit,rel         3   |   3/4     4/5     false / true
JNB     bit,rel         3   |   3/4     4/5     false / true
JBC     bit,rel         3   |   3/4     4/5     false / true
ACALL   addr19          3   |   4       4
LCALL   addr24          4   |   5       5
RET                     1   |   4       5
RETI                    1   |   4       5
AJMP    addr19          3   |   4       4
LJMP    addr24          4   |   5       5
SJMP    rel             2   |   3       3
JMP     @A+DPTR         1   |   2       2
JB      bit,rel         3   |   3/4     4/5     false / true
JNB     bit,rel         3   |   3/4     4/5     false / true
JBC     bit,rel         3   |   3/4     4/5     false / true
JC      rel             2   |   2/3     2/3     false / true
JNC     rel             2   |   2/3     2/3     false / true
JZ      rel             2   |   2/3     2/3     false / true
JNZ     rel             2   |   2/3     2/3     false / true
CJNE    A,direct, rel   3   |   3/4     4/5     false / true
CJNE    A,#data,rel     3   |   3/4     3/4     false / true
CJNE    Rr,#data,rel    3   |   3/4     3/4     false / true
CJNE    @Ri,#data,rel   3   |   3/4     3/4     false / true
DJNZ    Rr,rel          3   |   2/3     3/4     false / true
DJNZ    direct,rel      3   |   3/4     4/5     false / true
NOP                     1   |   1       1

Conditional jumps: condition is false / true
MOVX IXD / XDATA means: internal mapped xram / any external mapped xram
The extended stack works only withe internal mapped xram.